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features ? high-performance, low-power avr 8/16-bit xmega microcontroller ? non-volatile program and data memories ? 64k - 256k bytes of in-system self-programmable flash ? 4k - 8k boot code section with independent lock bits ? 2k - 4k bytes eeprom ? 4k - 16k bytes internal sram ? peripheral features ? four-channel dma controller with support for external requests ? eight-channel event system ? seven 16-bit timer/counters four timer/counters with 4 output compare or input capture channels three timer/counters wi th 2 output compare or input capture channels high resolution extensions on all timer/counters advanced waveform extension on one timer/counter ? seven usarts irda extension on 1 usart ? aes and des crypto engine ? two two-wire interfaces with dual address match(i 2 c and smbus compatible) ? three spi (serial peripheral interfaces) ? 16-bit real time counter with separate oscillator ? two eight-channel, 12-bit, 2 msps analog to digital converters ? one two-channel, 12-bit, 1 msps digital to analog converter ? four analog comparators wi th window compare function ? external interrupts on a ll general purpose i/o pins ? programmable watchdog timer with sepa rate on-chip ultra low power oscillator ? special microcontroller features ? power-on reset and programmable brown-out detection ? internal and external clock options with pll ? programmable multi-level interrupt controller ? sleep modes: idle, power-down, stan dby, power-save, extended standby ? advanced programming, test and debugging interfaces jtag (ieee 1149.1 compliant) interf ace for test, debug and programming pdi (program and debug interface) fo r programming, test and debugging ? i/o and packages ? 50 programmable i/o lines ? 64-lead tqfp ? 64-pad mlf ? operating voltage ? 1.6 ? 3.6v ? speed performance ? 0 ? 12 mhz @ 1.6 ? 3.6v ? 0 ? 32 mhz @ 2.7 ? 3.6v typical applications ? industrial control ? climate control ? hand-held battery applications ? factory automation ? zigbee ? power tools ? building control ? motor control ? hvac ? board control ? networking ? metering ? white goods ? optical ? medical applications 8/16-bit xmega a3 microcontroller atxmega256a3 atxmega192a3 ATXMEGA128A3 atxmega64a3 preliminary 8068e?avr?08/08
2 8068e?avr?08/08 xmega a3 1. ordering information notes: 1. this device can also be supplied in wafer form. please contact your local atmel sales office for detailed ordering info rmation. 2. pb-free packaging, complies to the european directive for restriction of hazardous substances (rohs directive). also halide f ree and fully green. 3. for packaging information, see ?packaging information? on page 66 . 2. pinout/block diagram figure 2-1. block diagram and tqfp-pinout. note: 1. for full details on pinout and alternate pin functions refer to ?pinout and pin functions? on page 48 . ordering code flash (b) e 2 (b) sram (b) speed (mhz) power supply package (1)(2)(3) temp atxmega256a3-au 256k + 8k 4k 16k 32 1.6 - 3.6v 64a -40 ? - 85 ? c atxmega192a3-au 192k + 8k 4k 16k 32 1.6 - 3.6v ATXMEGA128A3-au 128k + 8k 2k 8k 32 1.6 - 3.6v atxmega64a3-au 64k + 4k 2k 4k 32 1.6 - 3.6v atxmega256a3-mu 256k + 8k 4k 16k 32 1.6 - 3.6v 64m1 atxmega192a3-mu 192k + 8k 4k 16k 32 1.6 - 3.6v ATXMEGA128A3-mu 128k + 8k 2k 8k 32 1.6 - 3.6v atxmega64a3-mu 64k + 4k 2k 4k 32 1.6 - 3.6v package type 64a 64-lead, 14 x 14 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) 64m1 64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, 5.40 mm exposed pad, micro lead frame package (mlf) i n dex cor n er 17 1 8 19 20 21 22 23 24 25 26 27 2 8 29 30 31 32 64 63 62 61 60 59 5 8 57 56 55 54 53 52 51 50 49 4 8 47 46 45 44 43 42 41 40 39 3 8 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 pf2 pf1 pf0 v cc g n d pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 v cc g n d pd7 pa 3 pa 4 pa 5 pa 6 pa 7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 g n d v cc pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 g n d v cc pd0 pd1 pd2 pd3 pd4 pd5 pd6 pa 2 pa 1 pa 0 a v cc g n d pr1 pr0 reset/pdi_clk pdi_data pf7 pf6 v cc g n d pf5 pf4 pf3 flash ram e 2 prom dma interr u pt controller ocd adc a adc b dac b ac a0 ac a1 ac b0 ac b1 por t a port b e v ent system ctrl port r po w er control reset control watchdog osc/clk control bod por rtc e v e n t routi n g n etwork data bu s data bu s v ref temp port c port d port e port f cpu t/c0:1 usart0:1 spi twi t/c0:1 usart0:1 spi t/c0:1 usart0:1 spi twi t/c0 usart0
3 8068e?avr?08/08 xmega a3 3. overview the xmega a3 is a family of low power, high performance and peripheral rich cmos 8/16-bit microcontrollers based on the avr ? enhanced risc architecture. by executing powerful instructions in a single clock cycle, the xm ega a3 achieves throughputs approaching 1 million instructions per second (mips) per mhz allowing the system desi gner to optimi ze power con- sumption versus processing speed. the avr cpu combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instructi on, executed in one clock cycle. the resulting architecture is more code efficient while achi eving throughputs many times faster than conven- tional single-accumula tor or cisc based microcontrollers. the xmega a3 devices provide the following features: in-system programmable flash with read- w hile- w rite capabilities, internal eeprom and sram, four-channel dma controller, eight-channel event system, programmable multi-level interrupt controller, 50 general purpose i/o lines, 16-bit real time counter (rtc), sev en flexible 16-bit timer/counters with compare modes and p w m, seven usarts, two two w ire serial interfaces (t w is), three serial periph- eral interfaces (spis), aes and des crypto engine, two 8-channel 12-bit adcs with optional differential input with programmable gain, one 2-channel 12-bit dacs, four analog comparators with window mode, programmable w atchdog timer with separate internal oscillator, accurate internal oscillators with pll and presca ler and programmable brown-out detection. the program and debug interface (pdi), a fast 2-pin interface for programming and debugging, is available. the devices also have an ieee std. 1149.1 compliant jtag test interface, and this can also be used for on-chip debug and programming. the xmega a3 devices have five software selectable power saving modes. the idle mode stops the cpu while allo wing the sram, dma controller, even t system, interrupt controller and all peripherals to continue functioning. the power-down mode saves the sram and register contents but stops the oscillators, disabling all other functions until the next t w i or pin-change interrupt, or reset. in power-save mode, the asynchronous real time counter continues to run, allowing the application to maintain a timer base while the rest of the device is sleeping. in standby mode, the crystal/resonator oscillator is kept running while the rest of the device is sleeping. this allows very fast start-up from external crystal combined with low power consump- tion. in extended standby mode, both the main oscillator and the asynchronous timer continue to run. to further reduce power consumption, the peripheral clock for each individual peripheral can optionally be stopped in active mode and idle sleep mode. the device is manufactured using atmel's high-density nonvolatile memory technology. the pro- gram flash memory can be reprogrammed in-system through the pdi or jtag. a bootloader running in the device can use any interface to download the application program to the flash memory. the bootloader software in the boot flash section will continue to run while the appli- cation flash section is updated, providing true read- w hile- w rite operation. by combining an 8/16-bit risc cpu with in-syste m self-programmable flash, th e atmel xmega a3 is a power- ful microcontroller family that provides a highly flexible and cost effective solution for many embedded applications. the xmega a3 devices are supported with a full suite of program and system development tools including: c compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
4 8068e?avr?08/08 xmega a3 3.1 block diagram figure 3-1. xmega a3 block diagram pe[0..7] port e (8) tce0:1 usarte0:1 twie spie tcf0 usartf0 port f (8) power supervision por/bod & reset port a (8) port b (8) dma controller bus controller sram adca aca dacb adcb acb ocd internal reference pdi cpu pa[0..7] pb[0..7]/ jtag watchdog timer watchdog oscillator interrupt controller data bus data bus prog/debug controller vcc gnd oscillator circuits/ clock generation oscillator control real time counter event system controller jtag arefa arefb pdi_data reset/ pdi_clk port b sleep controller flash eeprom nvm controller des aes ircom port c (8) pc[0..7] tcc0:1 usartc0:1 twic spic pd[0..7] port r (2) xtal1 xtal2 pr[0..1] port d (8) tcd0:1 usartd0:1 spid tosc1 tosc2 event routing network pf[0..7] to clock generator
5 8068e?avr?08/08 xmega a3 4. resources a comprehensive set of development tools, app lication notes and datasheets are available for download on http:// www.atmel.com/avr. 4.1 recommended reading ? xmega a manual ? xmega a application notes this device data sheet only contains part specific information and a short description of each peripheral and module. the xmega a manual describes the modules and peripherals in depth. the xmega a application notes contain example code and show applied use of the modules and peripherals. the xmega a manual and application notes are available from http://www.atmel.com/avr. 5. disclaimer for devices that are not available yet, typica l values contained in this datasheet are based on simulations and characterization of other av r xmega microcontrollers manufactured on the same process technology. min. and max val ues will be available after the device is characterized.
6 8068e?avr?08/08 xmega a3 6. avr cpu 6.1 features ? 8/16-bit high performan ce avr risc architecture ? 138 instructions ? hardware multiplier ? 32x8-bit registers directly connected to the alu ? stack in ram ? stack pointer accessible in i/o memory space ? direct addressing of up to 16m bytes of program and data memory ? true 16/24-bit access to 16/24-bit i/o registers ? support for 8-, 16- and 32-bit arithmetic ? configuration change protection of system critical features 6.2 overview the xmega a3 uses an 8/16-bit avr cpu. the ma in function of the avr cpu is to ensure cor- rect program execution. the cpu must therefore be able to access memories, perform calculations and control peripherals. interrupt handling is described in a separate section. figure 6-1 on page 6 shows the cpu block diagram. figure 6-1. cpu block diagram the avr uses a harvard architecture - with separate memories and buses for program and data. instructions in the program memory are executed with a single level pipeline. w hile one instruction is being executed, the next instruction is pre-fetched from the program memory. flash program memory instruction decode program counter ocd 32 x 8 general purpose registers alu multiplier/ des instruction register status/ control peripheral module 1 peripheral module 2 eeprom pmic sram data bus data bus
7 8068e?avr?08/08 xmega a3 this concept enables instructions to be executed in every clock cycle. the program memory is in-system re-programmable flash memory. 6.3 register file the fast-access register file contains 32 x 8-bit general purpose working registers with a single clock cycle access time. this allows single-cycle ar ithmetic logic unit (alu ) operation. in a typ- ical alu operation, two operands are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock cycle. six of the 32 registers can be used as three 16-b it indirect address register pointers for data space addressing - enabling efficient address calculations. one of these address pointers can also be used as an address pointer for look up tables in flash program memory. 6.4 alu - arithmetic logic unit the high performance arithmetic logic unit (a lu) supports arithmetic and logic operations between registers or between a constant and a regi ster. single register operations can also be executed. w ithin a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. after an arithmetic or logic operation, the status register is updated to reflect information about the result of the operation. the alu operations are divided into three main categories ? arithmetic, logical, and bit-func- tions. both 8- and 16-bit arithmetic is supported, and the instruction set allows for easy implementation of 32-bit arithmetic. the alu also provides a powerful multiplier supporting both signed and unsigned multiplication and fractional format. 6.5 program flow w hen the device is powered on, the cpu starts to execute instructions from the lowest address in the flash program memory ?0?. the program counter (pc) addresses the next instruction to be fetched. after a reset, the pc is set to location ?0?. program flow is provided by conditional and unconditional jump and call instructions, capable of addressing the whole address space directly. most avr instructions use a 16-bit word format, while a limited number uses a 32-bit format. during interrupts and subroutine calls, the return address pc is stored on the stack. the stack is effectively allocated in the general data sram, and consequently the stack size is only limited by the total sram size and the usage of the sr am. after reset the stack pointer (sp) points to the highest address in the internal sram. the sp is read/write accessible in the i/o memory space, enabling easy implementation of multiple stacks or stack areas. the data sram can easily be accessed through the five different addressing modes supported in the avr cpu.
8 8068e?avr?08/08 xmega a3 7. memories 7.1 features ? flash program memory ? one linear address space ? in-system programmable ? self-programming and bootloader support ? application section for application code ? application table section for application code or data storage ? boot section for application code or bootloader code ? separate lock bits and protection for all sections ? data memory ? one linear address space ? single cycle access from cpu ? sram ? eeprom byte or page accessible optional memory mapping for direct load and store ? i/o memory configuration and status register for all peripherals and modules 16-bit accessible general purpose regi ster for global variables or flags ? external memory support ? bus arbitration safe and deterministic handling of cpu and dma controller priority ? separate buses for sram, eeprom, i/o memory and external memory access simultaneous bus access for cpu and dma controller ? calibration row memory for factory programmed data oscillator calibration bytes serial number device id for each device type ? user signature row one flash page in size can be read and written from software data is kept after chip erase 7.2 overview the avr architecture has two main memory s paces, the program memory and the data mem- ory. in addition, the xm ega a3 features an eepr om memory for non-vola tile data storage. all three memory spaces are linear and require no paging. the available me mory size configura- tions are shown in ?ordering information? on page 2 . in addition each device has a flash memory signature row for calibration data, device identification, serial number etc. non-volatile memory spaces can be locked for further write or read/write operations. this pre- vents unrestricted access to the application software.
9 8068e?avr?08/08 xmega a3 7.3 in-system programmable flash program memory the xmega a3 devices contains on-chip in-system programmable flash memory for program storage, see figure 7-1 on page 9 . since all avr instructions are 16- or 32-bits wide, each flash address location is 16 bits. the program flash memory space is divided into application and boot sections. both sections have dedicated lock bits for setting restrictions on write or read/write operations. the store pro- gram memory (spm) instruction must reside in the boot section when used to write to the flash memory. a third section inside the applicat ion section is referred to as the application table section which has separate lock bits for storage of write or read/write protection. the application table sec- tion can be used for storing non-volatile data or application software. the application table section and boot sect ion can also be used for general application software. figure 7-1. flash program memory (hexadecimal address) word address 0 application section (256k/192k/128k/64k) ... 1efff / 16fff / efff / 77ff 1f000 / 17000 / f000 / 7800 application table section (8k/8k/8k/4k) 1ffff / 17fff / ffff / 7fff 20000 / 18000 / 10000 / 8000 boot section (8k/8k/8k/4k) 20fff / 18fff / 10fff / 87ff
10 8068e?avr?08/08 xmega a3 7.4 data memory the data memory consist of the i/o memory, eeprom and sram memories, all within one lin- ear address space, see figure 7-2 on page 10 . to simplify development, the memory map for all devices in the family is identical and with empt y, reserved memory space for smaller devices. figure 7-2. data memory map (hexadecimal address) byte address atxmega192a3 byte address ATXMEGA128A3 byte address atxmega64a3 0 i/o registers (4kb) 0 i/o registers (4kb) 0 i/o registers (4kb) fff fff fff 1000 eeprom (4k) 1000 eeprom (2k) 1000 eeprom (2k) 17ff 17ff 1fff reserved reserved 2000 internal sram (16k) 2000 internal sram (8k) 2000 internal sram (4k) 5fff 3fff 2fff 6000 external memory (0 - 16 mb) 4000 external memory (0 - 16 mb) 3000 external memory (0 - 16 mb) ffffff ffffff ffffff byte address atxmega256a3 0 i/o registers (4kb) fff 1000 eeprom (4k) 1fff 2000 internal sram (16k) 5fff 6000 external memory (0 - 16 mb) ffffff
11 8068e?avr?08/08 xmega a3 7.4.1 i/o memory all peripherals and modules are addressable through i/o memory locations in the data memory space. all i/o memory locations can be accessed by the load (ld/lds/ldd) and store (st/sts/std) instructions, transferring data between the 32 general purpose registers in the cpu and the i/o memory. the in and out instructions can address i/o memory locations in the range 0x00 - 0x3f directly. i/o registers within the address range 0x00 - 0x1f are directly bit-acce ssible using the sbi and cbi instructions. the value of single bits can be checked by using the sbis and sbic instruc- tions on these registers. the i/o memory address for all peripherals and modules in xmega a3 is shown in the ?periph- eral module address map? on page 53 . 7.4.2 sram data memory the xmega a3 devices has internal sram memory for data storage. 7.4.3 eeprom data memory the xmega a3 devices has internal eeprom memory for non-volatile data storage. it is addressable either in a separate data space or it can be memory mapped into the normal data memory space. the eeprom memory supports both byte and page access.
12 8068e?avr?08/08 xmega a3 7.5 calibration row the calibration row is a separate memory section for factory programmed data. it contains cal- ibration data for functions such as oscillators, device id, and a factory programmed serial number that is unique for each device. the device id for the available xmega a3 devices is shown in table 7-1 on page 12 . some of the calibration values will be automatically loaded to the corresponding module or peripheral unit during reset. the calibration row can not be written or erased. it can be read from application software and external programming. table 7-1. device id bytes for xmega a3 devices. 7.6 user signature row the user signature row is a separate memory section that is fully accessible (read and write) from application software and external programming. the user signature row is one flash page in size, and is meant for static user parameter storage, such as calibration data, custom serial numbers, random number seeds etc. this section is not erased by chip erase, and requires a dedicated erase command. this ensures parameter storage during multiple program/erase ses- sion and on-chip debug sessions. device device id bytes byte 2 byte 1 byte 0 atxmega64a3 42 96 1e ATXMEGA128A3 42 97 1e atxmega192a3 44 97 1e atxmega256a3 42 98 1e
13 8068e?avr?08/08 xmega a3 7.7 flash and eeprom page size the flash program memory and eeprom data me mory is organized in pages. the pages are word accessible for the flash and byte accessible for the eeprom. table 7-2 on page 13 shows the flash program memory organization. flash write and erase operations are performed on one page at the time, while reading the flash is done one byte at the time. for flash access the z-pointer (z[m:n]) is used for addressing. the most significant bits in the address (fpage) gives the page nu mber and the least significant address bits (f w ord) gives the word in the page. table 7-2. number of words and pages in the flash. table 7-3 on page 13 shows eeprom memory organiza tion for the xmega a3 devices. eeeprom write and erase operation s can be performed on e page or one byte at the time, while reading the eeprom is done one byte at the time. for eeprom access the nvm address register (addr[m:n] is used for addressing. the most significant bits in the address (e2page) gives the page number and the least significant add ress bits (e2byte) gives the byte in the page. table 7-3. number of bytes and pages in the eeprom. devices flash page size fword fpage application boot size (bytes) (words) size no of pages size no of pages atxmega64a3 64k + 4k 128 z[7:1] z[16:8] 64k 256 4k 16 ATXMEGA128A3 128k + 8k 256 z[8:1] z[17:9] 128k 256 8k 16 atxmega192a3 192k + 8k 256 z[8:1] z[18:9] 192k 384 8k 16 atxmega256a3 256k + 8k 256 z[8:1] z[18:9] 256k 512 8k 16 devices eeprom page size e2byte e2page no of pages size (bytes) (bytes) atxmega64a3 2k 32 addr[4:0] addr[10:5] 64 ATXMEGA128A3 2k 32 addr[4:0] addr[10:5] 64 atxmega192a3 2k 32 addr[4:0] addr[10:5] 64 atxmega256a3 4k 32 addr[4:0] addr[11:5] 128
14 8068e?avr?08/08 xmega a3 8. dmac - direct memory access controller 8.1 features ? allows high-speed data transfer ? from memory to peripheral ? from memory to memory ? from peripheral to memory ? from peripheral to peripheral ? 4 channels ? from 1 byte and up to 16 m bytes transfers in a single transaction ? multiple addressing modes for so urce and destination address ?increment ? decrement ? static ? 1, 2, 4, or 8 bytes burst transfers ? programmable priority between channels 8.2 overview the xmega a3 has a direct memory access (dma) controller to move data between memories and peripherals in the data space. the dma controller uses the same data bus as the cpu to transfer data. it has 4 channels that can be configured independently. each dma channel can perform data transfers in blocks of configurable size from 1 to 64k bytes. a repeat counter can be used to repeat each block transfer for single transactions up to 16m bytes. each dma channel can be configured to access the source and destination memory address with incrementing, decrement- ing or static addressing. the addressing is independent for source and destination address. w hen the transaction is complete the original source and destination address can automatically be reloaded to be ready for the next transaction. the dmac can access all the peripherals through their i/o memory registers, and the dma may be used for automatic transfer of data to/from communication modules, as well as automatic data retrieval from adc conversions, data transfer to dac conversions, or data transfer to or from port pins. a wide range of transfer triggers is available from the peripherals, event system and software. each dma channel has different transfer triggers. to allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the first is finished and vice versa. the dma controller can read from memory ma pped eeprom, but it cannot write to the eeprom or access the flash.
15 8068e?avr?08/08 xmega a3 9. event system 9.1 features ? inter-peripheral communication and signalling with minimum latency ? cpu and dma independent operation ? 8 event channels allows for up to 8 signals to be rout ed at the same time ? events can be generated by ? timer/counters (tcxn) ? real time counter (rtc) ? analog to digital converters (adcx) ? analog comparators (acx) ? ports (portx) ? system clock (clk sys ) ? software (cpu) ? events can be used by ? timer/counters (tcxn) ? analog to digital converters (adcx) ? digital to analog converters (dacx) ? ports (portx) ? dma controller (dmac) ? ir communication module (ircom) ? the same event can be used by multip le peripherals for synchronized timing ? advanced features ? manual event generati on from software (cpu) ? quadrature decoding ? digital filtering ? functions in active and idle mode 9.2 overview the event system is a set of features for inter-peripheral communication. it enables the possibil- ity for a change of state in one peripheral to automatically trigger actions in one or more peripherals. w hat changes in a periph eral that will trigger actions in other peripherals are config- urable by software. it is a simple, but powerful system as it allows for autonomous control of peripherals without any use of interrupts, cpu or dma resources. the indication of a change in a peripheral is re ferred to as an event, and is usually the same as the interrupt conditions for that peripheral. events are passed between peripherals using a dedi- cated routing network called the event routing network. figure 9-1 on page 16 shows a basic block diagram of the event system with the event routing network and the peripherals to which it is connected. this highly flexible system can be used for simple routing of signals, pin func- tions or for sequencing of events. the maximum latency is two cpu clock cycles from when an event is generated in one periph- eral, until the actions are triggered in one or more other peripherals. the event system is functional in both active and idle modes.
16 8068e?avr?08/08 xmega a3 figure 9-1. event system block diagram. the event routing network can directly connect together adcs, dacs, analog comparators (acx), i/o ports (portx), the real-time counter (rtc), timer/counters (t/c) and the ir com- munication module (ircom). events can also be generated from software (cpu). all events from all peripherals are always routed into the event routing network. this consist of eight multiplexers where each can be configured in software to select which event to be routed into that event channel. all eight event channels are connected to the peripherals that can use events, and each of these peripherals can be co nfigured to use events from one or more event channels to automatically trigger a software selectable action. adcx dacx event routing network portx cpu acx rtc t/cxn dmac ircom clk sys
17 8068e?avr?08/08 xmega a3 10. system clock and clock options 10.1 features ? fast start-up time ? safe run-time clock switching ? internal oscillators: ? 32 mhz run-time cal ibrated rc oscillator ? 2 mhz run-time calibrated rc oscillator ? 32 khz calibrated rc oscillator ? 32 khz ultra low power (ulp) oscillator ? external clock options ? 0.4 - 16 mhz crystal oscillator ? 32 khz crystal oscillator ? external clock ? pll with internal and external clock options with 2 to 31x multiplication ? clock prescalers with 2 to 2048x division ? fast peripheral clock running at 2 and 4 times the cpu clock speed ? automatic run-time calibration of internal oscillators ? crystal oscillator failure detection 10.2 overview xmega a3 has an advanced clock system, supporting a large number of clock sources. it incor- porates both int egrated oscillators, external crystal osc illators and resonators . a high frequency phase locked loop (pll) and clock prescalers can be controlled from software to generate a wide range of clock frequencies from the clock source input. it is possible to switch between clock sources from software during run-time. after reset the device will always start up running fr om the 2 mhz inte rnal oscillator. a calibration feature is available, and can be used for automatic run-time calibration of the inter- nal 2 mhz and 32 mhz oscillators . this reduce frequency drift over voltage and temperature. a crystal oscillator failure m onitor can be enabled to issue a non-maskable interrupt and switch to internal oscillator if the external oscillator fails. figure 10-1 on page 18 shows the prin- cipal clock system in xmega a3.
18 8068e?avr?08/08 xmega a3 figure 10-1. clock system overview each clock source is briefly described in th e following sub-sections. 10.3 clock options 10.3.1 32 khz ultra low power internal oscillator the 32 khz ultra low power (ulp) internal oscillator is a very low power consumption clock source. it is used for the w atchdog timer, brown-out detecti on and as an asynchronous clock source for the real time counter. this oscill ator cannot be used as the system clock source, and it cannot be directly controlled from software. 10.3.2 32.768 khz calibrated internal oscillator the 32.768 khz calibrated internal oscillator is a high accuracy clock source that can be used as the system clock source or as an asynchronous clock source for the real time counter. it is calibrated during protection to provide a def ault frequency which is close to its nominal frequency. 32 mhz run-time calibrated internal oscillator 32 khz ulp internal oscillator 32.768 khz calibrated internal oscillator 32.768 khz crystal oscillator 0.4 - 16 mhz crystal oscillator 2 mhz run-time calibrated internal oscillator external clock input clock control unit with pll and prescaler wdt/bod clk ulp rtc clk rtc evsys peripherals adc dac ports ... clk per dma interrupt ram nvm memory flash eeprom cpu clk cpu
19 8068e?avr?08/08 xmega a3 10.3.3 32.768 khz crystal oscillator the 32.768 khz crystal oscillator is a low power driver for an external watch crystal. it can be used as system clock source or as asynchrono us clock source for the real time counter. 10.3.4 0.4 - 16 mhz crystal oscillator the 0.4 - 16 mhz crystal oscillator is a driver in tended for driving both external resonators and crystals ranging from 400 khz to 16 mhz. 10.3.5 2 mhz run-time calibrated internal oscillator the 2 mhz run-time calibrated internal oscillato r is a high frequency oscillator. it is calibrated during protection to provide a default frequency which is close to its nominal frequency. the oscillator can use the 32 khz calibra ted internal oscillato r or the 32 khz crys tal oscillator as a source for calibrating the frequency run-time to compensate for temperature and voltage drift hereby optimizing the ac curacy of the oscillator. 10.3.6 32 mhz run-time calibrated internal oscillator the 32 mhz run-time calibrated inte rnal oscillator is a high frequen cy oscillator. it is calibrated during protection to provide a default frequency which is close to its nominal frequency. the oscillator can use the 32 khz calibra ted internal oscillato r or the 32 khz crys tal oscillator as a source for calibrating the frequency run-time to compensate for temperature and voltage drift hereby optimizing the ac curacy of the oscillator. 10.3.7 external clock input the external clock input gives the possibility to connect a clock from an external source. 10.3.8 pll with multiplication factor 2 - 31x the pll provides the possibility of multiplying a frequency by any number from 2 to 31. in com- bination with the prescalers, this gives a wide range of output frequencies from all clock sources.
20 8068e?avr?08/08 xmega a3 11. power management and sleep modes 11.1 features ? 5 sleep modes ?idle ? power-down ?power-save ?standby ? extended standby ? power reduction registers to disable clocks to unused peripherals 11.2 overview the xmega a3 provides various sleep modes tailo red to reduce power consumption to a mini- mum. all sleep modes are available and can be entered from active mode. in active mode the cpu is executing application code. the applicat ion code decides when and what sleep mode to enter. interrupts from enabled peripherals and all enabled reset sources can restore the micro- controller from sleep to active mode. in addition, power reduction registers provide a method to stop the clock to individual peripher- als from software. w hen this is done, the current state of the peripheral is frozen and there is no power consumption from that peripheral. this reduces the power consumption in active mode and idle sleep mode. 11.3 sleep modes 11.3.1 idle mode in idle mode the cpu and non-volatile memory are stopped, but all peripherals including the interrupt controller, event system and dma controller are kept running. interrupt requests from all enabled in terrupts will wake the device. 11.3.2 power-down mode in power-down mode all system clock sources, and the asynchronous real time counter (rtc) clock source, are stopped. this allows operatio n of asynchronous modules only. the only inter- rupts that can wake up the mcu are the two w ire interface address match interrupts, and asynchronous port interrupts, e.g pin change. 11.3.3 power-save mode power-save mode is identical to power-down, with one exception: if the rtc is enabled, it will keep running during sleep and the device can also wake up from rtc interrupts. 11.3.4 standby mode standby mode is identical to power-down with the exception that all enabled system clock sources are kept running, while the cpu, periph eral and rtc clocks are stopped. this reduces the wake-up time when external crystals or resonators are used.
21 8068e?avr?08/08 xmega a3 11.3.5 extended standby mode extended standby mode is identical to power-sav e mode with the exception that all enabled system clock sources are kept ru nning while the cpu and periph eral clocks are stopped. this reduces the wake-up time when external crystals or resonators are used.
22 8068e?avr?08/08 xmega a3 12. system control and reset 12.1 features ? multiple reset sources for safe operation and device reset ? power-on reset ? external reset ? watchdog reset the watchdog timer runs from separate, dedica ted oscillator ? brown-out reset accurate, programmable brown-out levels ? jtag reset ? pdi reset ? software reset ? asynchronous reset ? no running clock in the device is required for reset ? reset status register 12.2 resetting the avr during reset, all i/o registers are set to their initial values. the sram content is not reset. appli- cation execution starts from the reset vector. the instruction placed at the reset vector should be an absolute jump (jmp) instruction to the reset handling routine. by default the reset vector address is the lowest flash program memory address, ?0?, but it is possible to move the reset vector to the first address in the boot section. the i/o ports of the avr are immediately tri-stated when a reset source goes active. the reset functionality is asynchronous, so no running clock is required to reset the device. after the device is reset, the reset source can be determined by the application by reading the reset status register. 12.3 reset sources 12.3.1 power-on reset the mcu is reset when the supp ly voltage vcc is below the po wer-on reset threshold voltage. 12.3.2 external reset the mcu is reset when a low leve l is present on the reset pin. 12.3.3 watchdog reset the mcu is reset when the w atchdog timer period expires and the w atchdog reset is enabled. the w atchdog timer runs from a dedicated oscillator independent of the system clock. for more details see ? w dt - w atchdog timer? on page 23 . 12.3.4 brown-out reset the mcu is reset when the supply voltage vcc is below the brown-out reset threshold voltage and the brown-out detector is enabled. the brown-out threshold voltage is programmable.
23 8068e?avr?08/08 xmega a3 12.3.5 jtag reset the mcu is reset as long as there is a logic one in the reset register in one of the scan chains of the jtag system. refer to ieee 11 49.1 (jtag) boundary -scan for details. 12.3.6 pdi reset the mcu can be reset through the program and debug interface (pdi). 12.3.7 software reset the mcu can be reset by the cpu writing to a special i/o register through a timed sequence. 12.4 wdt - watchdog timer 12.4.1 features ? 11 selectable timeout periods, from 8 ms to 8s. ? two operation modes ? standard mode ? window mode ? runs from the 1 khz output of th e 32 khz ultra low power oscillator ? configuration lock to prevent unwanted changes 12.4.2 overview the xmega a3 has a w atchdog timer ( w dt). the w dt will run continuous ly when turned on and if the w atchdog timer is not reset within a software configurable time-out period, the micro- controller will be reset. the w atchdog reset ( w dr) instruction must be ru n by software to reset the w dt, and prevent microcontroller reset. the w dt has a w indow mode. in this mode the w dr instruction must be run within a specified period called a window. application software can set the minimum and maximum limits for this window. if the w dr instruction is not executed inside t he window limits, the microcontroller will be reset. a protection mechanism using a timed write se quence is implemented in order to prevent unwanted enabling, disabling or change of w dt settings. for maximum safety, the w dt also has an always-on mode. this mode is enabled by program- ming a fuse. in always-on mode, application software can not disable the w dt.
24 8068e?avr?08/08 xmega a3 13. pmic - programmable mult i-level interrupt controller 13.1 features ? separate interrupt vector for each interrupt ? short, predictable in terrupt response time ? programmable multi-level interrupt controller ? 3 programmable interrupt levels ? selectable priority scheme within low level interrupts (round-robin or fixed) ? non-maskable interrupts (nmi) ? interrupt vectors can be moved to the start of the boot section 13.2 overview xmega a3 has a programmable multi-level interrupt controller (pmic). all peripherals can define three different priority levels for interrupts; high, medium or low. medium level interrupts may interrupt low level interrupt service routines. high level interrupts may interrupt both low- and medium level interrupt service routines. low level interrupts have an optional round robin scheme to make sure all interrupts are serviced within a certain amount of time. the built in oscillator failure detection mechanism can issue a non-maskable interrupt (nmi). 13.3 interrupt vectors w hen an interrupt is serviced, t he program counter will ju mp to the interrupt vector address. the interrupt vector is the sum of the peripheral?s base interrupt address and the offset address for specific interrupts in each peripheral. the base addresses for the xmega a3 devices are shown in table 13-1 . offset addresses for each interrupt available in the peripheral are described for each peripheral in the xmega a manual. for peripherals or modules that have only one inter- rupt, the interrupt vector is shown in table 13-1 . the program address is the word address. table 13-1. reset and interrupt vectors program address (base address) source interrupt description 0x000 reset 0x002 oscf_int_vect crystal oscillato r failure interrupt vector (nmi) 0x004 portc_int_base port c interrupt base 0x008 portr_int_base port r interrupt base 0x00c dmac_int_base dma controller interrupt base 0x014 rtc_int_base real time counter interrupt base 0x018 t w ic_int_base two- w ire interface on port c interrupt base 0x01c timerc0_int_base timer/counter 0 on port c interrupt base 0x028 timerc1_int_base timer/counter 1 on port c interrupt base 0x030 spic_int_vect spi on port c interrupt vector 0x032 usartc0_int_base usart 0 on port c interrupt base 0x03d usartc1_int_base usart 1 on port c interrupt base 0x03e aes_int_vect aes interrupt vector
25 8068e?avr?08/08 xmega a3 0x040 nvm_int_base non-volatile memory interrupt base 0x044 portb_int_base port b interrupt base 0x048 acb_int_base analog comparator on port b interrupt base 0x04e adcb_int_base analog to digital converter on port b interrupt base 0x056 porte_int_base port e int base 0x05a t w ie_int_base two- w ire interface on port e interrupt base 0x05e timere0_int_base timer/count er 0 on port e interrupt base 0x06a timere1_int_base timer/count er 1 on port e interrupt base 0x072 spie_int_vect spi on port e interrupt vector 0x074 usarte0_int_base usart 0 on port e interrupt base 0x07a usarte1_int_base usart 1 on port e interrupt base 0x080 portd_int_base port d interrupt base 0x084 porta_int_base port a interrupt base 0x088 aca_int_base analog comparator on port a interrupt base 0x08e adca_int_base analog to digital converter on port a interrupt base 0x09a timerd0_int_base timer/counter 0 on port d interrupt base 0x0a6 timerd1_int_base timer/counter 1 on port d interrupt base 0x0ae spid_int_vector spi d interrupt vector 0x0b0 usartd0_int_base usart 0 on port d interrupt base 0x0b6 usartd1_int_base usart 1 on port d interrupt base 0x0d0 portf_int_base port f interrupt base 0x0d8 timerf0_int_base timer/count er 0 on port f interrupt base 0x0ee usartf0_int_base usart 0 on port f interrupt base table 13-1. reset and interrupt vectors (continued) program address (base address) source interrupt description
26 8068e?avr?08/08 xmega a3 14. i/o ports 14.1 features ? selectable input and output configuration for each pin individually ? flexible pin configuration through dedicated pin configuration register ? synchronous and/or asynchronous input sensing with port interrupts and events ? sense both edges ? sense rising edges ? sense falling edges ? sense low level ? asynchronous wake-up from all input sensing configurations ? two port interrupts with flexible pin masking ? highly configurable output driver and pull settings: ? totem-pole ? pull-up/-down ? wired-and ? wired-or ? bus-keeper ? inverted i/o ? optional slew rate control ? configuration of multiple pins in a single operation ? read-modify-write (rmw) support ? toggle/clear/set registers for output and direction registers ? clock output on port pin ? event channel 7 output on port pin ? mapping of port registers (virtual port s) into bit accessible i/o memory space 14.2 overview the xmega a3 devices have flexible general purpose i/o ports. a port consists of up to 8 pins, ranging from pin 0 to pin 7. the ports implemen t several functions, including synchronous/asyn- chronous input sensing, pin change interrupts and configurable output settings. all functions are individual per pin, but several pins may be configured in a single operation. 14.3 i/o configuration all port pins (pn) have programmable output configuration. in addition, all port pins have an inverted i/o function. for an input, this means in verting the signal between the port pin and the pin register. for an output, this means invert ing the output signal between the port register and the port pin. the inverted i/o function can be used also when the pin is used for alternate func- tions. the port pins also have configurable sl ew rate limitation to reduce electromagnetic emission.
27 8068e?avr?08/08 xmega a3 14.3.1 push-pull figure 14-1. i/o configuration - totem-pole 14.3.2 pull-down figure 14-2. i/o configuration - totem-pole with pull-down (on input) 14.3.3 pull-up figure 14-3. i/o configuration - totem-pole with pull-up (on input) 14.3.4 bus-keeper the bus-keeper?s weak output produces the same logi cal level as the last output level. it acts as a pull-up if the last leve l was ?1?, and pull-down if the last level was ?0?. inn outn dirn pn inn outn dirn pn inn outn dirn pn
28 8068e?avr?08/08 xmega a3 figure 14-4. i/o configuration - totem-pole with bus-keeper 14.3.5 others figure 14-5. output configuration - w ired-or with optional pull-down figure 14-6. i/o configuration - w ired-and with optional pull-up inn outn dirn pn inn outn pn inn outn pn
29 8068e?avr?08/08 xmega a3 14.4 input sensing ? sense both edges ? sense rising edges ? sense falling edges ? sense low level input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is shown in figure 14-7 on page 29 . figure 14-7. input sensing system overview w hen a pin is configured with inverted i/o the pin value is inverted before the input sensing. 14.5 port interrupt each ports have two interrupts with separate priority and interrupt vector. all pins on the port can be individually selected as source for each of the interrupts. the interrupts are then triggered according to the input sense configuration for each pin configured as source for the interrupt. 14.6 alternate port functions in addition to the input/output functions on all po rt pins, most pins have alternate functions. this means that other modules or peripherals connected to the port can use the port pins for their functions, such as communication or pulse-width modulation. ?pinout and pin functions? on page 48 shows which modules on peripherals that enables alternate functions on a pin, and what alternate functions that is available on a pin. inverted i/o interrupt control ireq event pn d q r d q r synchronizer inn edge detect asynchronous sensing synchronous sensing edge detect
30 8068e?avr?08/08 xmega a3 15. t/c - 16-bits time r/counter with pwm 15.1 features ? seven 16-bit timer/counters ? four timer/counters of type 0 ? three timer/counters of type 1 ? four compare or capture (cc) channels in timer/counter 0 ? two compare or capture (cc) channels in timer/counter 1 ? double buffered timer period setting ? double buffered compare or capture channels ? waveform generation: ? single slope pulse width modulation ? dual slope pulse width modulation ? frequency generation ? input capture: ? input capture with noise cancelling ? frequency capture ? pulse width capture ? 32-bit input capture ? event counter with direction control ? timer overflow and timer error interrupts and events ? one compare match or capture interrupt and event per cc channel ? supports dma operation ? hi-resolution extension (hi-res) ? advanced waveform extension (awex) 15.2 overview xmega a3 has seven timer/counters, four timer/counter 0 and three timer/counter 1. the difference between them is that timer/counter 0 has four compare/capture channels, while timer/counter 1 has two compare/capture channels. the timer/counters (t/c) are 16-bit and can count any clock, event or external input in the microcontroller. a programmable prescaler is available to get a useful t/c resolution. updates of timer and compare registers are double buffered to ensure glitch free operation. single slope p w m, dual slope p w m and frequency generation waveforms can be generated using the com- pare channels. through the event system, any input pin or event in the microcontroller can be used to trigger input capture, hence no dedicated pins is requir ed for this. the input capture has a noise cancel- ler to avoid incorrect capture of the t/c, and can be used to do frequency and pulse width measurements. a wide range of interrupt or event sources ar e available, including t/c overflow, compare match and capture for each compare/capture channel in the t/c. portc, portd and porte each has one timer/counter 0 and one timer/counter1. portf has one timer/counter 0. notation of these are tcc0 (time/counter c0), tcc1, tcd0, tcd1, tce0, tce1 and tcf0, respectively.
31 8068e?avr?08/08 xmega a3 figure 15-1. overview of a timer/counter and closely related peripherals the hi-resolution extension can be enabled to increase the waveform generation resolution by 2 bits (4x). this is available for all timer/counters. see ?hi-res - high resolution extension? on page 33 for more details. the advanced w aveform extension can be enabled to provide extra and more advanced fea- tures for the timer/counter. this are only available for timer/counter 0. see ?a w ex - advanced w aveform extension? on page 32 for more details. awex compare/capture channel d compare/capture channel c compare/capture channel b compare/capture channel a waveform generation buffer comparator hi-res fault protection capture control base counter counter control logic timer period prescaler dti dead-time insertion pattern generation clk per4 port event system clk per timer/counter
32 8068e?avr?08/08 xmega a3 16. awex - advanced waveform extension 16.1 features ? output with complementary output from each capture channel ? four dead time insertion (dti) un its, one for each capture channel ? 8-bit dti resolution ? separate high and low side dead-time setting ? double buffered dead-time ? event controlled fault protection ? single channel multiple output operation (for bldc motor control) ? double buffered pattern generation 16.2 overview the advanced w aveform extension (a w ex) provides extra features to the timer/counter in w aveform generation ( w g) modes. the a w ex enables easy and safe implementation of for example, advanced motor control (ac, bldc, sr , and stepper) and power control applications. any w g output from a timer/counter 0 is split into a complimentary pair of outputs when any a w ex feature is enabled. these output pairs go through a dead-time insertion (dti) unit that enables generation of the non-inverted low side (ls) and inverted high side (hs) of the w g output with dead time insertion between ls and hs switching. the dti output will override the normal port value according to the port override setting. optionally the final output can be inverted by using the invert i/o setting for the port pin. the pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. in addition, the waveform generator output from compare channel a can be dis- tributed to, and override all port pins. w hen the pattern generator unit is enabled, the dti unit is bypassed. the fault protection unit is connected to the ev ent system. this enables any event to trigger a fault condition that will disable the a w ex output. several event channels can be used to trigger fault on several different conditions. the a w ex is available for tcc0. the notation of this is a w exc.
33 8068e?avr?08/08 xmega a3 17. hi-res - high r esolution extension 17.1 features ? increases waveform generator resolution by 2-bits (4x) ? supports frequency, single- and dual-slope pwm operation ? supports the awex when this is enable d and used for the same timer/counter 17.2 overview the hi-resolution (hi-res) extension is able to increase the resolution of the waveform genera- tion output by a factor of 4. w hen enabled for a timer/counter, the fast peripheral clock running at four times the cpu clock speed will be as input to th e timer/counter. the high resolution extension can also be used when an a w ex is enabled and used with a timer/counter. xmega a3 devices have four hi-res extensions that each can be enabled for each timer/counters pair on portc, portd, porte and portf. the notation of these are hiresc, hiresd, hirese and hiresf, respectively.
34 8068e?avr?08/08 xmega a3 18. rtc - real-time counter 18.1 features ? 16-bit timer ? flexible tick resolution ranging from 1 hz to 32.768 khz ? one compare register ? one period register ? clear timer on overflow or compare match ? overflow or compare match event and interrupt generation 18.2 overview the xmega a3 includes a 16-bit real-time count er (rtc). the rtc can be clocked from an accurate 32.768 khz crystal osc illator, the 32.768 khz ca librated internal osc illator, or from the 32 khz ultra low power internal oscillator. the rtc includes both a period and a compare register. for details, see figure 18-1 . a wide range of resolution and time-out periods can be configured using the rtc. w ith a max- imum resolution of 30.5 s, time-out periods range up to 2000 seconds. w ith a resolution of 1 second, the maximum time-out period is over 18 hours (65536 seconds). figure 18-1. real-time counter overview 10-bit prescaler counter period compare = = overflow compare match 1 khz 32 khz
35 8068e?avr?08/08 xmega a3 19. twi - two wire interface 19.1 features ? two identical twi peripherals ? simple yet powerful and flexible communication interface ? both master and sla ve operation supported ? device can operate as transmitter or receiver ? 7-bit address space allows up to 128 different slave addresses ? multi-master arbitration support ? up to 400 khz data transfer speed ? slew-rate limited output drivers ? noise suppression circuitry rejects spikes on bus lines ? fully programmable slave address with general call support ? address recognition causes w ake-up when in sleep mode ? i 2 c and system management bus (smbus) compatible 19.2 overview the two- w ire interface (t w i) is a bi-directional wired-and bus with only two lines, the clock (scl) line and the data (sda) line. the protocol makes it possible to interconnect up to 128 indi- vidually addressable devices. since it is a mult i-master bus, one or more devices capable of taking control of the bus can be connected. the only external hardware needed to implement the bus is a single pull-up resistor for each of the t w i bus lines. mechanisms for resolving bus contention are inherent in the t w i protocol. portc and porte each has one t w i. notation of these peripherals are t w ic and t w ie.
36 8068e?avr?08/08 xmega a3 20. spi - serial peripheral interface 20.1 features ? three identical spi peripherals ? full-duplex, three-wire synchronous data transfer ? master or slave operation ? lsb first or msb first data transfer ? seven programmable bit rates ? end of transmission interrupt flag ? write collision flag protection ? wake-up from idle mode ? double speed (ck/2) master spi mode 20.2 overview the serial peripheral interface (spi) allows high-speed full-duplex, synchronous data transfer between different devices. devices can communica te using a master-slave scheme, and data is transferred both to and from the devices simultaneously. portc, portd, and porte each has one spi. notation of these peripherals are spic, spid, and spie respectively.
37 8068e?avr?08/08 xmega a3 21. usart 21.1 features ? seven identical usart peripherals ? full duplex operation (independent se rial receive and transmit registers) ? asynchronous or synchronous operation ? master or slave clocked synchronous operation ? high-resolution arithmetic baud rate generator ? supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits ? odd or even parity generation and parity check supported by hardware ? data overrun detection ? framing error detection ? noise filtering includes false start bit detection and digital low pass filter ? three separate interrupts on tx complete, tx data register empty and rx complete ? multi-processor communication mode ? double speed asynchronous communication mode ? master spi mode for spi communication ? irda support through the ircom module 21.2 overview the universal synchronous and asynchronous serial receiver and transmitter (usart) is a highly flexible serial communica tion module. the usart supports full duplex communication, and both asynchronous and clocked synchronous operation. the usart can also be set in master spi mode to be used for spi communication. communication is frame based, and the frame format can be customized to support a wide range of standards. the usart is buffered in both direction, enabling continued data transmis- sion without any delay between frames. there are separate interrupt vectors for receive and transmit complete, enabling fully interrupt driven communication. frame error and buffer over- flow are detected in hardware and indicated with separate status flags. even or odd parity generation and parity check can also be enabled. one usart can use the ircom module to suppor t irda 1.4 physical compliant pulse modula- tion and demodulation for baud rates up to 115.2 kbps. portc, portd, and porte each has two usarts, while portf has one usart only. notation of these peripherals are usartc0, usartc1, usartd0, usartd1, usarte0, usarte1 and usartf0, respectively.
38 8068e?avr?08/08 xmega a3 22. ircom - ir communication module 22.1 features ? pulse modulation/demodulation for infrared communication ? compatible to irda 1.4 physical for baud rates up to 115.2 kbps ? selectable pulse modulation scheme ? 3/16 of baud rate period ? fixed pulse period, 8-bit programmable ? pulse modulation disabled ? built in filtering ? can be connected to and used by one usart at the time 22.2 overview xmega contains an infrared communication module (ircom) for irda communication with baud rates up to 115.2 kbps. this supports three modulation schemes: 3/16 of baud rate period, fixed programmable pulse time based on the peripheral clock speed, or pulse modulation dis- abled. there is one ircom available which can be connected to any usart to enable infrared pulse coding/decoding for that usart.
39 8068e?avr?08/08 xmega a3 23. crypto engine 23.1 features ? data encryption standard (des) cpu instruction ? advanced encryption stan dard (aes) crypto module ? des instruction ? encryption and decryption ? single-cycle des instruction ? encryption/decryption in 16 clock cycles per 8-byte block ? aes crypto module ? encryption and decryption ? support 128-bit keys ? support xor data load mode to the state memory for cipher block chaining ? encryption/decryption in 375 clock cycles per 16-byte block 23.2 overview the advanced encrypti on standard (aes) and da ta encryption standar d (des) are two com- monly used encryption st andards. these ar e supported through an aes peripheral module and a des cpu instruction. all communication inte rfaces and the cpu ca n optionally use aes and des encrypted communication and data storage. des is supported by a des instruction in the avr xmega cpu. the 8-byte key and 8-byte data blocks must be loade d into the register file, and then des must be executed 16 times to encrypt/decrypt the data block. the aes crypto module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. the key and data must be loaded into the key and state memory in the module before encryp- tion/decryption is started. it takes 375 peripheral clock cycles before the encryption/decryption is done and decrypted/encrypted data can be read out, and an optional interrupt can be generated. the aes crypto module also has dma support wit h transfer triggers wh en encryption/decryp- tion is done and optional auto-start of encryption/decryption when the state memory is fully loaded.
40 8068e?avr?08/08 xmega a3 24. adc - 12-bit analog to digital converter 24.1 features ? two adcs with 12-bit resolution ? 2 msps sample rate for each adc ? signed and unsign ed conversions ? 4 result registers with individual input channel control for each adc ? 8 single ended inputs for each adc ? 8x4 differential inputs for each adc ? software selectable gain of 2, 4, 8, 16, 32 or 64 ? software selectable resolution of 8- or 12-bit. ? internal or external reference selection ? event triggered conversion for accurate timing ? dma transfer of conversion results ? interrupt/event on compare result 24.2 overview xmega a3 devices have two analog to digital converters (adc), see figure 24-1 on page 41 . the two adc modules can be operated simult aneously, individually or synchronized. the adc converts analog voltages to digital values. the adc has 12-bit resolution and is capa- ble of converting up to 2 millio n samples per second. the input selection is flexible, and both single-ended and differential measurements can be performed. the adc can provide both signed and unsigned results, and an optional gain stage is available to increase the dynamic range of the adc. it is a successive approximation result (sar ) adc. a sar adc measures one bit of the con- version result at a time. the adc has a pipel ine architecture. this means that a new analog voltage can be sampled and a new adc measurem ent started on each adc clock cycle. each sample will be converted in the pipeline, where the total sample and conversion time is seven adc clock cycles for 12-bit result an d 5 adc clock cycles for 8-bit result. adc measurements can be started by application software or an incoming event from another peripheral in the device. four different result registers with individual channel selection (mux registers) are provided to make it easier for the application to keep track of the data. it is also possible to use dma to move adc result s directly to memory or peripherals. both internal and external analog reference volt ages can be used. an accurate internal 1.0v reference is available.
41 8068e?avr?08/08 xmega a3 figure 24-1. adc overview each adc has four mux selection registers with a corresponding result register. this means that four channels can be sampled within 1.5 s without any intervention by the application other than starting the conversion . the results will be availabl e in the result registers. the adc may be configured for 8- or 12-bit result, reducing the minimum conversion time (prop- agation delay) from 3.5 s for 12-bit to 2.5 s for 8-bit result. adc conversion results are provided left- or right adjusted with optional ?1? or ?0? padding. this eases calculation when the result is represented as a signed integer (signed 16-bit number). porta and portb each has one adc. notation of these peripherals are adca and adcb, respectively. adc channel a register channel b register channel c register channel d register pin inputs pin inputs 1-64 x internal inputs channel a mux selection channel b mux selection channel c mux selection channel d mux selection event trigger configuration reference selection
42 8068e?avr?08/08 xmega a3 25. dac - 12-bit digital to analog converter 25.1 features ? one dac with 12-bit resolution ? up to 1 msps conversion rate for each dac ? flexible conversion range ? multiple trigger sources ? 1 continuous output or 2 sample and hold (s/h) outputs for each dac ? built-in offset an d gain calibration ? high drive capabilities ? low power mode 25.2 overview the xmega a3 devices features two 12-bit, 1 ms ps dacs with built-in offset and gain calibra- tion, see figure 25-1 on page 42 . a dac converts a digital value into an anal og signal. the dac may use an internal 1.1 voltage as the upper limit for conversion, but it is also possible to use the supply voltage or any applied voltage in-between. the external reference input is shared with the adc reference input. figure 25-1. dac overview each dac has one continuous output with high dr ive capabilities for both resistive and capaci- tive loads. it is also possible to split the continuous time channel into two sample and hold (s/h) channels, each with separate data conversion registers. a dac conversion may be started from the applic ation software by writing the data conversion registers. the dac can also be configured to do conversions triggered by the event system to have regular timing, independent of the application software. dma may be used for transferring data from memory locations to dac data registers. the dac has a built-in calibration system to reduce offset and gain error when loading with a calibration value from software. portb each has one dac. notation of this peripheral is dacb. dac channel a register channel b register event trigger configuration reference selection channel a channel b
43 8068e?avr?08/08 xmega a3 26. ac - analog comparator 26.1 features ? four analog comparators ? selectable power vs. speed ? selectable hysteresis ? 0, 20 mv, 50 mv ? analog comparator output available on pin ? flexible input selection ? all pins on the port ? output from the dac ? bandgap reference voltage. ? voltage scaler that can perform a 64-le vel scaling of the internal vcc voltage. ? interrupt and event generation on ? rising edge ? falling edge ?toggle ? window function interrupt and event generation on ? signal above window ? signal inside window ? signal below window 26.2 overview xmega a3 features four analog comparators (ac). an analog comparator compares two volt- ages, and the output indicates which input is largest. the analog comparator may be configured to give interrupt requests and/or events upon several different combinations of input change. both hysteresis and propagation delays may be adjusted in order to find the optimal operation for each application. a wide range of input selection is available, both external pins and several internal signals can be used. the analog comparators are always grouped in pairs (ac0 and ac1) on each analog port. they have identical behavior but separate control registers. optionally, the state of the comparator is directly available on a pin. porta and portb each has one ac pair. notations are aca and acb, respectively.
44 8068e?avr?08/08 xmega a3 figure 26-1. analog comparator overview ac0 + - pin inputs internal inputs pin inputs internal inputs vcc scaled interrupt sensitivity control interrupts ac1 + - pin inputs internal inputs pin inputs internal inputs vcc scaled events pin 0 output
45 8068e?avr?08/08 xmega a3 26.3 input selection the analog comparators have a very flexible input selection and the two comparators grouped in a pair may be used to realize a window function. one pair of analog comparators is shown in figure 26-1 on page 44 . ? input selection from pin ? pin 0, 1, 2, 3, 4, 5, 6 selectable to positive input of analog comparator ? pin 0, 1, 3, 5, 7 selectable to negative input of analog comparator ? internal signals available on positive analog comparator inputs ? output from 12-bit dac ? internal signals available on ne gative analog comparator inputs ? 64-level scaler of the vcc, available on negative analog comparator input ? bandgap voltage reference ? output from 12-bit dac 26.4 window function the window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in figure 26-2 . figure 26-2. analog comparator window function ac0 + - ac1 + - input signal upper limit of window lower limit of window interrupt sensitivity control interrupts events
46 8068e?avr?08/08 xmega a3 27. ocd - on-chip debug 27.1 features ? complete program flow control ? go, stop, reset, step into, step over, step out, run-to-cursor ? debugging on c and high-level language source code level ? debugging on assembler and disassembler level ? 1 dedicated program address or source level breakpoint for avr studio / debugger ? 4 hardware breakpoints ? unlimited number of user program breakpoints ? unlimited number of user data breakpoints, with break on: ? data location read, write or both read and write ? data location content equal or not equal to a value ? data location content is greater or less than a value ? data location content is within or outside a range ? bits of a data location are eq ual or not equal to a value ? non-intrusive operation ? no hardware or software resources in the device are used ? high speed operation ? no limitation on debug/programming clock frequency versus sys tem clock frequency 27.2 overview the xmega a3 has a powerful on-chip debug (ocd) system that - in combination with atmel?s development tools - provides all the necessary functions to debug an application. it has support for program and data breakpoints, and can debug an application from c and high level language source code level, as well as assembler and disassembler level. it has full non-intrusive opera- tion and no hardware or softw are resources in the device are used. the odc system is accessed through an external debugging tool which connects to the jtag or pdi physical inter- faces. refer to ?program and debug interfaces? on page 47 .
47 8068e?avr?08/08 xmega a3 28. program and debug interfaces 28.1 features ? pdi - program and debug interface (atmel proprietary 2-pin interface) ? jtag interface (ieee std. 1149.1 compliant) ? boundary-scan capabilities according to the ieee std. 1149.1 (jtag) ? access to the ocd system ? programming of flash, eepr om, fuses and lock bits 28.2 overview the programming and debug facilities are accessed through the jtag and pdi physical inter- faces. the pdi physical uses one dedicated pin together with the reset pin, and no general purpose pins are used. jtag uses f our general purpose pins on portb. 28.3 jtag interface the jtag physical layer handles the basic low-level serial communication over four i/o lines named tms, tck, tdi, and tdo. it complies to the ieee std. 1149.1 for test access port and boundary scan. 28.4 pdi - program and debug interface the pdi is an atmel proprietary protocol for communication between the microcontroller and atmel?s development tools.
48 8068e?avr?08/08 xmega a3 29. pinout and pin functions the pinout of xmega a3 is shown in ?for packaging information, see ?packaging information? on page 66.? on page 2 . in addition to general i/o functionality, each pin may have several func- tion. this will depend on which per ipheral is enabled a nd connected to the actual pin. only one of the alternate pin functions can be used at time. 29.1 alternate pin f unction description the tables below show the notation for all pin functions available and describe its function. 29.1.1 operation/power supply 29.1.2 port interrupt functions 29.1.3 analog functions vcc digital supply voltage avcc analog supply voltage gnd ground sync port pin with full synchronous and limited asynchronous interrupt function async port pin with full syn chronous and full asynchro nous interrupt function acn analog comparator input pin n ac0out analog comparator 0 output adcn analog to digital converter input pin n dacn digital to analog converter output pin n aref analog reference input pin
49 8068e?avr?08/08 xmega a3 29.1.4 timer/counter and awex functions 29.1.5 communication functions 29.1.6 oscillators, clock and event 29.1.7 debug/system functions ocnx output compare channel x for timer/counter n ocxn inverted output compare channel x for timer/counter n scl serial clock for t w i sda serial data for t w i sclin serial clock in for t w i when external driver interface is enabled sclout serial clock out for t w i when external driver interface is enabled sdain serial data in for t w i when external driver interface is enabled sdaout serial data out for t w i when external driver interface is enabled xckn transfer clock for usart n rxdn receiver data for usart n txdn transmitter data for usart n ss slave select for spi mosi master out slave in for spi miso master in slave out for spi sck serial clock for spi toscn timer oscillator pin n xtaln input/output for inverting oscillator pin n clkout peripheral clock output evout event channel 0 output reset reset pin pdi_clk program and debug interface clock pin pdi_data program and debug interface data pin t c k j tag te s t c l o c k tdi jtag test data in t d o j tag te s t d a t a o u t t m s j tag te s t m o d e s e l e c t
50 8068e?avr?08/08 xmega a3 29.2 alternate pin functions the tables below show the main and alternate pin functions for all pins on each port. they also show which peripheral that makes use of or enables the alternate pin function. table 29-1. port a - alternate functions port a pin # interrupt adca pos adca neg adaa gainpos adca gainneg aca pos aca neg aca out refa gnd 60 avcc 61 pa0 62 sync adc0 adc0 adc0 ac0 ac0 arefa pa1 63 sync adc1 adc1 adc1 ac1 ac1 pa2 64 sync/async adc2 adc2 adc2 ac2 pa3 1 sync adc3 adc3 adc3 ac3 ac3 pa4 2 sync adc4 adc4 adc4 ac4 pa5 3 sync adc5 adc5 adc5 ac5 ac5 pa6 4 sync adc6 adc6 adc6 ac6 pa7 5 sync adc7 adc7 adc7 ac7 ac0 out table 29-2. port b - alternate functions port b pin # interrupt adcb pos adcb neg adcb gainpos adcb gainneg acb pos acb neg acb out dacb refb jtag pb0 6 sync adc0 adc0 adc0 ac0 ac0 arefb pb1 6 sync adc1 adc1 adc1 ac1 ac1 pb2 8 sync/async adc2 adc2 adc2 ac2 dac0 pb3 9 sync adc3 adc3 adc3 ac3 ac3 dac1 pb4 10 sync adc4 adc4 adc4 ac4 tms pb5 11 sync adc5 adc5 adc5 ac5 ac5 tdi pb6 12 sync adc6 adc6 adc6 ac6 tck pb7 13 sync adc7 adc7 adc7 ac7 ac0 out tdo gnd 14 vcc 15
51 8068e?avr?08/08 xmega a3 table 29-3. port c - alternate functions port c pin # interrupt tcc0 awexc tcc1 us artc0 usartc1 spic twic clockout eventout pc0 16 sync oc0a oc0a sda pc1 17 sync oc0b oc0a xck0 scl pc2 18 sync/async oc0c oc0b rxd0 pc3 19 sync oc0d oc0b txd0 pc4 20 sync oc0c oc1a ss pc5 21 sync oc0c oc1b xck1 mosi pc6 22 sync oc0d rxd1 miso pc7 23 sync oc0d txd1 sck clkout evout gnd 24 vcc 25 table 29-4. port d - alternate functions port d pin # interrupt tcd0 tcd1 usartd0 usartd1 spid clockout eventout pd0 26 sync oc0a pd1 27 sync oc0b xck0 pd2 28 sync/async oc0c rxd0 pd3 29 sync oc0d txd0 pd4 30 sync oc1a ss pd5 31 sync oc1b xck1 mosi pd6 32 sync rxd1 miso pd7 33 sync txd1 sck clkout evout gnd 34 vcc 35 table 29-5. port e - alternate functions port e pin # interrupt tce0 tce1 usarte0 usarte1 spie twie clockout eventout tosc pe0 36 sync oc0a sda pe1 37 sync oc0b xck0 scl pe2 38 sync/async oc0c rxd0 pe3 39 sync oc0d txd0 pe4 40 sync oc1a ss pe5 41 sync oc1b xck1 mosi pe6 42 sync rxd1 miso tosc1 pe7 43 sync txd1 sck clkout evout tosc1 gnd 44 vcc 45
52 8068e?avr?08/08 xmega a3 table 29-7. port r - alternate functions table 29-6. port f - alternate functions port f pin # interrupt tcf0 usartf0 pf0 46 sync oc0a pf1 47 sync oc0b xck0 pf2 48 sync/async oc0c rxd0 pf3 49 sync oc0d txd0 pf4 50 sync pf5 51 sync pf6 54 sync pf7 55 sync gnd 52 vcc 53 port r pin # interrupt progr xtal pdi 56 pdi_data reset 57 pdi_clock pro 58 sync xtal2 pr1 59 sync xtal1
53 8068e?avr?08/08 xmega a3 30. peripheral modu le address map the address maps show the base address for each peripheral and module in xmega a3. for complete register description and summary for each peripheral module, refer to the xmega a manual. base address name description 0x0000 gpio general purpose io registers 0x0010 vport0 virtual port 0 0x0014 vport1 virtual port 1 0x0018 vport2 virtual port 2 0x001c vport3 virtual port 2 0x0030 cpu cpu 0x0040 clk clock control 0x0048 sleep sleep controller 0x0050 osc oscillator control 0x0060 dfllrc32m dfll for the 32 mhz internal rc oscillator 0x0068 dfllrc2m dfll for the 2 mhz rc oscillator 0x0070 pr power reduction 0x0078 rst reset controller 0x0080 w dt w atch-dog timer 0x0090 mcu mcu control 0x00a0 pmic programmable multilevel interrupt controller 0x00b0 portcfg port configuration 0x00c0 aes aes module 0x0100 dma dma controller 0x0180 evsys event system 0x01c0 nvm non volatile memory (nvm) controller 0x0200 adca analog to digital converter on port a 0x0240 adcb analog to digital converter on port b 0x0320 dacb digital to analog converter on port b 0x0380 aca analog comparator pair on port a 0x0390 acb analog comparator pair on port b 0x0400 rtc real time counter 0x0480 t w ic two w ire interface on port c 0x04a0 t w ie two w ire interfaceon port e 0x0600 porta port a 0x0620 portb port b 0x0640 portc port c 0x0660 portd port d 0x0680 porte port e 0x06a0 portf port f 0x07e0 portr port r 0x0800 tcc0 timer/counter 0 on port c 0x0840 tcc1 timer/counter 1 on port c 0x0880 a w exc advanced w aveform extension on port c 0x0890 hiresc high resolution extension on port c 0x08a0 usartc0 usart 0 on port c 0x08b0 usartc1 usart 1 on port c 0x08c0 spic serial peripheral interface on port c 0x08f8 ircom infrared communication module 0x0900 tcd0 timer/counter 0 on port d 0x0940 tcd1 timer/counter 1 on port d 0x0990 hiresd high resolution extension on port d 0x09a0 usartd0 usart 0 on port d 0x09b0 usartd1 usart 1 on port d 0x09c0 spid serial peripheral interface on port d 0x0a00 tce0 timer/counter 0 on port e 0x0a40 tce1 timer/counter 1 on port e 0x0a80 a w exe advanced w aveform extensionon port e 0x0a90 hirese high resolution extension on port e 0x0aa0 usarte0 usart 0 on port e 0x0ab0 usarte1 usart 1 on oirt e 0x0ac0 spie serial peripheral interface on port e 0x0b00 tcf0 timer/counter 0 on port f 0x0b90 hiresf high resolution extension on port f 0x0ba0 usartf0 usart 0 on port f
54 8068e?avr?08/08 xmega a3 31. interrupt vector summary. 31.1 usart interrupt vectors 31.2 timer/counter interrupt vectors note: 1. only available on timer/counter with 4 compare or capture channels 16-bit. 31.3 spi interrupt vectors 31.4 twi interrupt vectors table 31-1. usart interrupt vectors offset source interr upt description 0 rxc usart receive complete interrupt vector offset 2 dre usart data register em pty interrupt vector offset 4 txc usart transmit complete interrupt vector offset table 31-2. timer/counter interrupt vectors offset source interrupt description 0 ovf timer/counter overflow/underflow interrupt vector offset 2 err timer/counter error interrupt vector offset 4 cca timer/counter compare or capture channel a interrupt vector offset 6 ccb timer/counter compare or capture channel b interrupt vector offset 8ccc (1) timer/counter compare or capture channel c interrupt vector offset 0x0a ccd (1) timer/counter compare or capture channel d interrupt vector offset table 31-3. spi interrupt vectors offset source interr upt description 0 spi spi interrupt vector offset table 31-4. t w i interrupt vectors offset source interr upt description 0mastert w i master interrupt vector offset 2slavet w i slave interrupt vector offset
55 8068e?avr?08/08 xmega a3 31.5 dma interrupt vectors 31.6 crystal oscillator failure interrupt vector 31.7 rtc interrupt vectors 31.8 aes interrupt vector 31.9 nvm interrupt vectors table 31-5. dma interrupt vectors offset source interr upt description 0 ch0 dma controller channel 0 interrupt vector offset 2 ch1 dma controller channel 1 interrupt vector offset 4 ch2 dma controller channel 2 interrupt vector offset 6 ch3 dma controller channel 3 interrupt vector offset table 31-6. crystal oscillator failu re interrupt vector offset source interr upt description 0 oscf crystal oscillator failure interrupt vector (nmi) offset table 31-7. rtc interrupt vectors offset source interr upt description 0 comp real time counter compare match interrupt vector offset 2 per real time counter period interrupt vector offset table 31-8. aes interrupt vector offset source interr upt description 0 aes aes interrupt vector offset table 31-9. nvm interrupt vectors offset source interr upt description 0 spm non-volatile memory spm interrupt level vector offset 2 ee non-volatile memory eeprom interrupt level vector offset
56 8068e?avr?08/08 xmega a3 31.10 analog comparator interrupt vectors 31.11 adc interrupt vectors 31.12 ports interrupt vectors table 31-10. analog comparator interrupt vectors offset source interr upt description 0 comp0 analog comparator 0 interrupt vector offset 2 comp1 analog comparator 1 interrupt vector offset 4 w indo w analog comparator w indow interrupt vector offset table 31-11. analog to digital converter interrupt vectors offset source interr upt description 0 ch0 analog to digital converter channel 0 interrupt vector offset 2 ch1 analog to digital converter channel 1 interrupt vector offset 4 ch2 analog to digital converter channel 2 interrupt vector offset 6 ch3 analog to digital converter channel 3 interrupt vector offset table 31-12. ports interrupt vectors offset source interr upt description 0 int0 port interrupt vector 0 offset 2 int1 port interrupt vector 1 offset
57 8068e?avr?08/08 xmega a3 32. instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add without carry rd rd + rr z,c,n,v,s,h 1 adc rd, rr add with carry rd rd + rr + c z,c,n,v,s,h 1 adi w rd, k add immediate to w ord rd rd + 1:rd + k z,c,n,v,s 2 sub rd, rr subtract without carry rd rd - rr z,c,n,v,s,h 1 subi rd, k subtract immediate rd rd - k z,c,n,v,s,h 1 sbc rd, rr subtract with carry rd rd - rr - c z,c,n,v,s,h 1 sbci rd, k subtract immediate with carry rd rd - k - c z,c,n,v,s,h 1 sbi w rd, k subtract immediate from w ord rd + 1:rd rd + 1:rd - k z,c,n,v,s 2 and rd, rr logical and rd rd ? rr z,n,v,s 1 andi rd, k logical and with immediate rd rd ? k z,n,v,s 1 or rd, rr logical or rd rd v rr z,n,v,s 1 ori rd, k logical or with immediate rd rd v k z,n,v,s 1 eor rd, rr exclusive or rd rd rr z,n,v,s 1 com rd one?s complement rd $ff - rd z,c,n,v,s 1 neg rd two?s complement rd $00 - rd z,c,n,v,s,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v,s 1 cbr rd,k clear bit(s) in register rd rd ? ($ffh - k) z,n,v,s 1 inc rd increment rd rd + 1 z,n,v,s 1 dec rd decrement rd rd - 1 z,n,v,s 1 tst rd test for zero or minus rd rd ? rd z,n,v,s 1 clr rd clear register rd rd rd z,n,v,s 1 ser rd set register rd $ff none 1 mul rd,rr multiply unsigned r1:r0 rd x rr (uu) z,c 2 muls rd,rr multiply signed r1:r0 rd x rr (ss) z,c 2 mulsu rd,rr multiply signed with unsigned r1:r0 rd x rr (su) z,c 2 fmul rd,rr fractional multiply unsigned r1:r0 rd x rr<<1 (uu) z,c 2 fmuls rd,rr fractional multiply signed r1:r0 rd x rr<<1 (ss) z,c 2 fmulsu rd,rr fractional multiply signed with unsigned r1:r0 rd x rr<<1 (su) z,c 2 des k data encryption if (h = 0) then r15:r0 else if (h = 1) then r15:r0 encrypt(r15:r0, k) decrypt(r15:r0, k) 1/2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc(15:0) pc(21:16) z, 0 none 2 eijmp extended indirect jump to (z) pc(15:0) pc(21:16) z, eind none 2 jmp k jump pc k none 3 rcall k relative call subroutine pc pc + k + 1 none 2 / 3 (1) icall indirect call to (z) pc(15:0) pc(21:16) z, 0 none 2 / 3 (1) eicall extended indirect call to (z) pc(15:0) pc(21:16) z, eind none 3 (1)
58 8068e?avr?08/08 xmega a3 call k call subroutine pc k none 3 / 4 (1) ret subroutine return pc stack none 4 / 5 (1) reti interrupt return pc stack i 4 / 5 (1) cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1 / 2 / 3 cp rd,rr compare rd - rr z,c,n,v,s,h 1 cpc rd,rr compare with carry rd - rr - c z,c,n,v,s,h 1 cpi rd,k compare with immediate rd - k z,c,n,v,s,h 1 sbrc rr, b skip if bit in register cleared if (rr(b) = 0) pc pc + 2 or 3 none 1 / 2 / 3 sbrs rr, b skip if bit in register set if (rr(b) = 1) pc pc + 2 or 3 none 1 / 2 / 3 sbic a, b skip if bit in i/o register cleared if (i/o(a,b) = 0) pc pc + 2 or 3 none 2 / 3 / 4 sbis a, b skip if bit in i/o register set if (i/o(a,b) =1) pc pc + 2 or 3 none 2 / 3 / 4 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc + k + 1 none 1 / 2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc + k + 1 none 1 / 2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1 / 2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1 / 2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1 / 2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1 / 2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1 / 2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1 / 2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1 / 2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1 / 2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1 / 2 brlt k branch if less than, signed if (n v= 1) then pc pc + k + 1 none 1 / 2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1 / 2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1 / 2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1 / 2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1 / 2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1 / 2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1 / 2 brie k branch if interrupt enabled if (i = 1) then pc pc + k + 1 none 1 / 2 brid k branch if interrupt disabled if (i = 0) then pc pc + k + 1 none 1 / 2 data transfer instructions mov rd, rr copy register rd rr none 1 mov w rd, rr copy register pair rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd k none 1 lds rd, k load direct from data space rd (k) none 2 (1)(2) ld rd, x load indirect rd (x) none 1 (1)(2) ld rd, x+ load indirect and post-increment rd x (x) x + 1 none 1 (1)(2) ld rd, -x load indirect and pre-decrement x x - 1, rd (x) x - 1 (x) none 2 (1)(2) ld rd, y load indirect rd (y) (y) none 1 (1)(2) ld rd, y+ load indirect and post-increment rd y (y) y + 1 none 1 (1)(2) mnemonics operands description operation flags #clocks
59 8068e?avr?08/08 xmega a3 ld rd, -y load indirect and pre-decrement y rd y - 1 (y) none 2 (1)(2) ldd rd, y+q load indirect with displacement rd (y + q) none 2 (1)(2) ld rd, z load indirect rd (z) none 1 (1)(2) ld rd, z+ load indirect and post-increment rd z (z), z+1 none 1 (1)(2) ld rd, -z load indirect and pre-decrement z rd z - 1, (z) none 2 (1)(2) ldd rd, z+q load indirect with displacement rd (z + q) none 2 (1)(2) sts k, rr store direct to data space (k) rd none 2 (1) st x, rr store indirect (x) rr none 1 (1) st x+, rr store indirect and post-increment (x) x rr, x + 1 none 1 (1) st -x, rr store indirect and pre-decrement x (x) x - 1, rr none 2 (1) st y, rr store indirect (y) rr none 1 (1) st y+, rr store indirect and post-increment (y) y rr, y + 1 none 1 (1) st -y, rr store indirect and pre-decrement y (y) y - 1, rr none 2 (1) std y+q, rr store indirect with displacement (y + q) rr none 2 (1) st z, rr store indirect (z) rr none 1 (1) st z+, rr store indirect and post-increment (z) z rr z + 1 none 1 (1) st -z, rr store indirect and pre-decrement z z - 1 none 2 (1) std z+q,rr store indirect with displacement (z + q) rr none 2 (1) lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-increment rd z (z), z + 1 none 3 elpm extended load program memory r0 (rampz:z) none 3 elpm rd, z extended load program memory rd (rampz:z) none 3 elpm rd, z+ extended load program memory and post- increment rd z (rampz:z), z + 1 none 3 spm store program memory (rampz:z) r1:r0 none - spm z+ store program memory and post-increment by 2 (rampz:z) z r1:r0, z + 2 none - in rd, a in from i/o location rd i/o(a) none 1 out a, rr out to i/o location i/o(a) rr none 1 push rr push register on stack stack rr none 1 (1) pop rd pop register from stack rd stack none 2 (1) bit and bit-test instructions lsl rd logical shift left rd(n+1) rd(0) c rd(n), 0, rd(7) z,c,n,v,h 1 lsr rd logical shift right rd(n) rd(7) c rd(n+1), 0, rd(0) z,c,n,v 1 mnemonics operands description operation flags #clocks
60 8068e?avr?08/08 xmega a3 notes: 1. cycle times for data memo ry accesses assume internal memo ry accesses, and are not valid for accesses via the external ram interface. 2. one extra cycle must be added when accessing internal sram. rol rd rotate left through carry rd(0) rd(n+1) c c, rd(n), rd(7) z,c,n,v,h 1 ror rd rotate right through carry rd(7) rd(n) c c, rd(n+1), rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 s w ap rd swap nibbles rd(3..0) ? rd(7..4) none 1 bset s flag set sreg(s) 1sreg(s)1 bclr s flag clear sreg(s) 0sreg(s)1 sbi a, b set bit in i/o register i/o(a, b) 1 none 1 cbi a, b clear bit in i/o register i/o(a, b) 0 none 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) t none 1 sec set carry c 1c1 clc clear carry c 0c1 sen set negative flag n 1n1 cln clear negative flag n 0n1 sez set zero flag z 1z1 clz clear zero flag z 0z1 sei global interrupt enable i 1i1 cli global interrupt disable i 0i1 ses set signed test flag s 1s1 cls clear signed test flag s 0s1 sev set two?s complement overflow v 1v1 clv clear two?s complement overflow v 0v1 set set t in sreg t 1t1 clt clear t in sreg t 0t1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0h1 mcu control instructions break break (see specific descr. for break) none 1 nop no operation none 1 sleep sleep (see specific descr. for sleep) none 1 w dr w atchdog reset (see specific descr. for w dr) none 1 mnemonics operands description operation flags #clocks
61 8068e?avr?08/08 xmega a3 33. electrical characteristics - tbd 33.1 absolute maximum ratings* 33.2 dc characteristics note: 1. ?max? means the highest value where the pin is guaranteed to be read as low 2. ?min? means the lowest value where t he pin is guaranteed to be read as high operating temperature....................................-55 ? c to +125 ? c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of th is specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .......................................-65 ? c to +150 ? c voltage on any pin with respect to ground..-0.5v to v cc +0.5v maximum operating voltage ............................................ 3.6v dc current per i/o pin ............................................... 20.0 ma dc current v cc and gnd pins................................ 200.0 ma t a = -40 ? c to 85 ? c, v cc = 1.6v to 3.6v (unless otherwise noted) symbol parameter condition min. typ. max. units v il input low voltage, except xtal1 pin v v il1 input low voltage, xtal1 pins v v ih input high voltage, except xtal1 pin v v ih1 input high voltage, xtal1 pin v v ol output low voltage v oh output high voltage i il input leakage current i/o pin a i ih input leakage current i/o pin a r rst reset pull-up resistor k r pu i/o pin pull-up resistor k i cc power supply current active 32 mhz ma active 20 mhz ma active 8mhz ma idle 32 mhz ma idle 20 mhz ma power-down mode w dt disabled a w dt slow sampling a w dt fast sampling
62 8068e?avr?08/08 xmega a3 33.3 speed the maximum frequency of the xmega a3 dev ices is depending on vcc. as shown in figure 33-1 on page 62 the frequency vs. vcc curve is linear between 1.8v < vcc < 2.7v. figure 33-1. maximum frequency vs. vcc 1. 8 12 32 mhz v 2.7 3.6 1.6 safe operating area
63 8068e?avr?08/08 xmega a3 33.4 adc characteristics ? tbd table 33-1. adc characteristics symbol parameter condition min typ max units resolution lsb integral non-linearity (inl) lsb differential non-linearity (dnl) lsb gain error lsb offset error lsb conversion time s adc clock frequency mhz dc supply voltage ma source impedance start-up time s avcc analog supply voltage vcc - 0.3 vcc + 0.3 v table 33-2. adc gain stage characteristics symbol parameter condition min typ max units gain input capacitance pf offset error mv gain error % signal range v dc supply current ma start-up time # clk cycles
64 8068e?avr?08/08 xmega a3 33.5 dac characteristics ? tbd 33.6 analog comparator characteristics ? tbd table 33-3. dac characteristics symbol parameter condition min typ max units resolution lsb integral non-linearity (inl) lsb differential non-linearity (dnl) lsb gain error lsb offset error lsb calibrated gain/offset error lsb output range v output settling time s output capacitance nf output resistance k reference input voltage v reference input capacitance pf reference input resistance k current consumption ma start-up time s table 33-4. analog comparator characteristics symbol parameter condi tion min typ max units offset mv hysteresis no mv low high propagation delay high speed mode ns low power mode current consumption high speed mode a low power mode start-up time s
65 8068e?avr?08/08 xmega a3 34. typical characteristics - tbd
66 8068e?avr?08/08 xmega a3 35. packaging information 35.1 64a 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 44a, 44-lead, 10 x 10 mm body size, 1.0 mm body thickness, 0.8 mm lead pitch, thin profile plastic quad flat package (tqfp) b 44a 10/5/2001 pin 1 identifier 0?~7? pin 1 l c a1 a2 a d1 d e e1 e b common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-026, variation acb. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25 mm per side. dimensions d1 and e1 are maximum plastic body size dimensions including mold mismatch. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 11.75 12.00 12.25 d1 9.90 10.00 10.10 note 2 e 11.75 12.00 12.25 e1 9.90 10.00 10.10 note 2 b 0.30 ? 0.45 c 0.09 ? 0.20 l 0.45 ? 0.75 e 0.80 typ
67 8068e?avr?08/08 xmega a3 35.2 64m1 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 64m1 , 64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, g 64m1 5/25/06 common dimen s ion s (unit of measure = mm) s ymbol min nom max note a 0.80 0.90 1.00 a1 ? 0.02 0.05 b 0.18 0.25 0.30 d d2 5.20 5.40 5.60 8.90 9.00 9.10 8.90 9.00 9.10 e e2 5.20 5.40 5.60 e 0.50 bsc l 0.35 0.40 0.45 note: 1. jedec standard mo-220, (saw singulation) fig. 1, vmmd. 2. dimension and tolerance conform to asmey14.5m-1994. top view s ide view bottom view d e marked pin# 1 id seating plane a1 c a c 0.08 1 2 3 k 1.25 1.40 1.55 e2 d2 b e pin #1 corner l pin #1 triangle pin #1 chamfer (c 0.30) option a option b pin #1 notch (0.20 r) option c k k 5.40 mm exposed pad, micro lead frame package (mlf)
68 8068e?avr?08/08 xmega a3 36. errata 36.1 all rev. no known errata.
69 8068e?avr?08/08 xmega a3 37. datasheet revision history 37.1 8068e ? 08/08 37.2 8068d ? 06/08 37.3 8068c ? 06/08 37.4 8068b ? 06/08 1. updated ?block diagram? on page 4 . 2. inserted ?interrupt vector summary.? on page 54 . 1. references to external bus interface (ebi) removed from ?features? on page 1 . 1. updated ?features? on page 1 . 2. updated figure 2-1 on page 2 . 3. updated ?overview? on page 3 . 4. updated table 7-2 on page 13 . 5. replaced figure 24-1 on page 41 by a correct one. 6. updated ?features? and ?overview? on page 42 . 7. updated all tables in section ?alternate pin functions? on page 50 . 1. updated ?features? on page 1 . 2. updated ?for packaging information, see ?packaging information? on page 66.? on page 2 and ?pinout and pin functions? on page 48 . 3. updated ?ordering information? on page 2 . 4. updated ?overview? on page 3 , included the xmega a3 explanation text on page 6. 5. added xmega a3 block diagram, figure 3-1 on page 4 . 6. updated avr cpu ?overview? on page 6 and updated figure 6-1 on page 6 . 7. updated event system block diagram, figure 9-1 on page 16 . 8. updated ?pmic - programmable multi-level interrupt controller? on page 24 . 9. updated ?ac - analog comparator? on page 43 .
70 8068e?avr?08/08 xmega a3 37.5 8068a ? 02/08 10. updated ?i/o configuration? on page 26 . 11. inserted a new figure 15-1 on page 31 . 12. updated ?peripheral module address map? on page 53 . 13. inserted ?instruction set summary? on page 57 . 14. added speed grades in ?speed? on page 62 . 1. initial revision.
i 8068e?avr?08/08 xmega a3 table of contents features ................ ................ .............. .............. .............. .............. ............. 1 typical applications .............. .............. .............. .............. .............. .......... 1 1 ordering information .......... .............. .............. .............. .............. ............. 2 2 pinout/block diagram ......... .............. .............. .............. .............. ............. 2 3 overview ............ ................ ................ .............. .............. .............. ............. 3 3.1block diagram ...........................................................................................................4 4 resources .............. .............. .............. .............. .............. .............. ............. 5 4.1recommended reading .............................................................................................5 5 disclaimer .............. .............. .............. .............. .............. .............. ............. 5 6 avr cpu ................ .............. .............. .............. .............. .............. ............. 6 6.1features ................................................................................................................... .6 6.2overview ................................................................................................................... .6 6.3register file .............................................................................................................. 7 6.4alu - arithmetic logic unit .......................................................................................7 6.5program flow ............................................................................................................7 7 memories ............... .............. .............. .............. .............. .............. ............. 8 7.1features ................................................................................................................... .8 7.2overview ................................................................................................................... .8 7.3in-system programmable flash program memory ...................................................9 7.4data memory ...........................................................................................................10 7.5calibration row .......................................................................................................12 7.6user signature row ................................................................................................12 7.7flash and eeprom page size ...............................................................................13 8 dmac - direct memory access controller ............... ................ ........... 14 8.1features ..................................................................................................................1 4 8.2overview ..................................................................................................................1 4 9 event system ......... .............. .............. .............. .............. .............. ........... 15 9.1features ..................................................................................................................1 5 9.2overview ..................................................................................................................1 5 10 system clock and clock op tions .................. .............. .............. ........... 17 10.1features ................................................................................................................17
ii 8068e?avr?08/08 xmega a3 10.2overview ................................................................................................................17 10.3clock options ........................................................................................................18 11 power management and sleep modes ........ ................ .............. ........... 20 11.1features ................................................................................................................20 11.2overview ................................................................................................................20 11.3sleep modes ..........................................................................................................20 12 system control and reset .... .............. .............. .............. .............. ........ 22 12.1features ................................................................................................................22 12.2resetting the avr .................................................................................................22 12.3reset sources .......................................................................................................22 12.4 w dt - w atchdog timer .........................................................................................23 13 pmic - programmable mult i-level interrupt controller ............ ........... 24 13.1features ................................................................................................................24 13.2overview ................................................................................................................24 13.3interrupt vectors .....................................................................................................24 14 i/o ports ............... ................ .............. .............. .............. .............. ........... 26 14.1features ................................................................................................................26 14.2overview ................................................................................................................26 14.3i/o configuration ....................................................................................................26 14.4input sensing .........................................................................................................29 14.5port interrupt ..........................................................................................................29 14.6alternate port functions ........................................................................................29 15 t/c - 16-bits timer/counter with pwm .......... .............. .............. ........... 30 15.1features ................................................................................................................30 15.2overview ................................................................................................................30 16 awex - advanced waveform ex tension ........... .............. ............ ........ 32 16.1features ................................................................................................................32 16.2overview ................................................................................................................32 17 hi-res - high resolut ion extension .......... ................ ................ ........... 33 17.1features ................................................................................................................33 17.2overview ................................................................................................................33 18 rtc - real-time counter .... .............. .............. .............. .............. ........... 34 18.1features ................................................................................................................34
iii 8068e?avr?08/08 xmega a3 18.2overview ................................................................................................................34 19 twi - two wire interface ........... ................. ................ ................ ........... 35 19.1features ................................................................................................................35 19.2overview ................................................................................................................35 20 spi - serial peripheral interface ............ .............. .............. ............ ........ 36 20.1features ................................................................................................................36 20.2overview ................................................................................................................36 21 usart ............. ................. ................ ................ .............. .............. ........... 37 21.1features ................................................................................................................37 21.2overview ................................................................................................................37 22 ircom - ir communi cation module .......... ................ ................ ........... 38 22.1features ................................................................................................................38 22.2overview ................................................................................................................38 23 crypto engine ........... ................ ................ ................. ................ ............. 39 23.1features ................................................................................................................39 23.2overview ................................................................................................................39 24 adc - 12-bit analog to di gital converter ...... .............. .............. ........... 40 24.1features ................................................................................................................40 24.2overview ................................................................................................................40 25 dac - 12-bit digital to an alog converter ...... .............. .............. ........... 42 25.1features ................................................................................................................42 25.2overview ................................................................................................................42 26 ac - analog comparator .... .............. .............. .............. .............. ........... 43 26.1features ................................................................................................................43 26.2overview ................................................................................................................43 26.3input selection .......................................................................................................45 26.4 w indow function ...................................................................................................45 27 ocd - on-chip debug ............ .............. .............. .............. .............. ........ 46 27.1features ................................................................................................................46 27.2overview ................................................................................................................46 28 program and debug interfaces ............... ................. ................ ............. 47 28.1features ................................................................................................................47 28.2overview ................................................................................................................47
iv 8068e?avr?08/08 xmega a3 28.3jtag interface .......................................................................................................47 28.4pdi - program and debug interface ......................................................................47 29 pinout and pin functions ................. .............. .............. .............. ........... 48 29.1alternate pin function description ........................................................................48 29.2alternate pin functions .........................................................................................50 30 peripheral module address map ................... .............. .............. ........... 53 31 interrupt vector summary. . .............. .............. .............. .............. ........... 54 31.1usart interrupt vectors .......................................................................................54 31.2timer/counter interrupt vectors .............................................................................54 31.3spi interrupt vectors ..............................................................................................54 31.4t w i interrupt vectors .............................................................................................54 31.5dma interrupt vectors ............................................................................................55 31.6crystal oscillator failure interrupt vector ..............................................................55 31.7rtc interrupt vectors ............................................................................................55 31.8aes interrupt vector ................. ................ ................ ................ ................ .............55 31.9nvm interrupt vectors ............................................................................................55 31.10analog comparator interrupt vectors ..................................................................56 31.11adc interrupt vectors ..........................................................................................56 31.12ports interrupt vectors .....................................................................................56 32 instruction set summary .... .............. .............. .............. .............. ........... 57 33 electrical characteristics - tbd ............ .............. .............. ............ ........ 61 33.1absolute maximum ratings* .................................................................................61 33.2dc characteristics .................................................................................................61 33.3speed ....................................................................................................................6 2 33.4adc characteristics ? tbd ...................................................................................63 33.5dac characteristics ? tbd ...................................................................................64 33.6analog comparator characteristics ? tbd ...........................................................64 34 typical characteristics - tbd ................. ................. ................ ............. 65 35 packaging information .......... .............. .............. .............. .............. ........ 66 35.164a ....................................................................................................................... .66 35.264m1 ...................................................................................................................... 67 36 errata ............. ................ ................. ................ ................ .............. ........... 68 36.1all rev. .................................................................................................................. ..68
v 8068e?avr?08/08 xmega a3 37 datasheet revision history ... .............. .............. .............. .............. ........ 69 37.18068e ? 08/08 .......................................................................................................69 37.28068d ? 06/08 .......................................................................................................69 37.38068c ? 06/08 .......................................................................................................69 37.48068b ? 06/08 .......................................................................................................69 37.58068a ? 02/08 .......................................................................................................70 table of contents.......... ................. ................ ................ ................. ........... i
8068e?avr?08/08 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en- yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support avr@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life. ? 2008 atmel corporation. all rights reserved. atmel ? , logo and combinations thereof, avr ? and others are registered trademarks, xmega tm and others are trademarks of atmel corporation or its subsidia ries. other terms and product names may be trademarks of others.

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